Ayar Labs has announced the introduction of the industry’s first Universal Chiplet Interconnect Express™ (UCIe™) optical interconnect chiplet, designed to maximize performance and efficiency in AI infrastructures by significantly reducing latency and power consumption. Incorporating a UCIe electrical interface, Ayar Labs’ TeraPHY™ optical I/O chiplet offers 8 Tbps bandwidth, powered by the company’s 16-wavelength SuperNova™ light source.
By supporting the UCIe standard, Ayar Labs’ optical interconnect facilitates interoperability among chiplets from different manufacturers, creating a cost-effective and accessible ecosystem. This compatibility simplifies integration, reduces design complexity, and accelerates the deployment of advanced optical technologies critical for scaling AI workloads.
“Optical interconnects are needed to solve power density challenges in scale-up AI fabrics,” said Mark Wade, CEO and co-founder of Ayar Labs. “We recognized early on the potential for co-packaged optics, which positioned us to drive adoption of optical solutions in AI applications. As we continue to push the boundaries of optical technologies, we’re also bringing together the supply chain, manufacturing, and testing and validation processes needed for customers to deploy these solutions at scale.”
Ayar Labs’ optical chiplet integrates silicon photonics with CMOS manufacturing processes, enabling efficient optical interconnects within multi-chip packages. This allows GPUs and accelerators to communicate seamlessly across distances ranging from millimeters to kilometers, functioning effectively as a single GPU unit.
About UCIe™:
UCIe™ (Universal Chiplet Interconnect Express™) is an open specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.
The UCIe Consortium is supported by Board members Alibaba, AMD, Arm, Advanced Semiconductor Engineering, Inc. (ASE), Google Cloud, Intel Corporation, Meta, Microsoft, NVIDIA, Qualcomm Incorporated, Samsung, and Taiwan Semiconductor Manufacturing Company, along with extensive Contributor and Promoter memberships. Together, these organizations aim to establish a robust global ecosystem for chiplet design.
Initial focus areas of the UCIe standard include:
- Physical Layer: Die-to-Die I/O with industry-leading performance indicators
- Protocol: CXL/PCIe for near-term volume attach
- Well-defined specification: Ensuring interoperability and evolution
Future goals of the UCIe standard include additional protocols, advanced chiplet form factors, chiplet management capabilities, and expanded functionality.
Statements from UCIe Consortium Members:
- Advanced Micro Devices (AMD): “As the leader in chiplet technology, we are proud to continue our long history of supporting industry standards that drive innovation forward and create solutions to meet our customers’ and the industry’s needs,” said Mark Papermaster, Chief Technology Officer and Executive Vice President, AMD. “The robust, open, and vendor-neutral chiplet ecosystem provided by UCIe is critical to meeting the challenge of scaling networking solutions to deliver on the full potential of AI. We’re excited that Ayar Labs is one of the first deployments that leverages the UCIe platform to its full extent.”
- Advanced Semiconductor Engineering (ASE): “Our ecosystem is deeply immersed in the development of interoperable chiplet solutions to support the rapid progress towards tomorrow’s AI infrastructure and accelerated compute requirements,” said Dr. CP Hung, Vice President of R&D at ASE, Inc. “UCIe is playing a significant role, and through fostering interoperability and collaboration, it is driving standards that elevate efficiency and performance. ASE commends Ayar Labs’ contribution to the CPO momentum with the world’s first UCIe optical I/O chiplet.”
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Alphawave Semi: “Alphawave Semi is proud to be a leader in advancing novel optical interconnect solutions that drive the future of AI infrastructure with Ayar Labs. This groundbreaking achievement will be the first instance of multi-vendor, multi-foundry UCIe subsystem silicon interoperability targeted for optical connectivity, enabling unparalleled performance in AI scale-up architectures. The seamless integration with AlphaCHIP1600-IO, our 1.6Tb electrical I/O chiplet, will eliminate data bottlenecks and enhance system efficiency built on a foundation of our best-in-class low latency and power efficient UCIe IP.” said Letizia Giuliano, Vice President of Product Marketing and Management.
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d-Matrix: “d-Matrix is building inference AI accelerators for the datacenter market using 2D/3D chiplet technology that dramatically improves interactivity and throughput,” said Sid Sheth, Founder & CEO of d-Matrix. “Optical connectivity is critical to solving network bottlenecks as we scale-out our compute accelerators. The chiplet ecosystem depends on open standards and accessible products, and we are excited to see Ayar Labs bring the first UCIe optical chiplet to market.”
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GlobalFoundries: “As the industry transitions to a chiplet-based approach to system partitioning, the UCIe interface for chiplet-to-chiplet communication is rapidly becoming a de facto standard,” said Kevin Soukup, senior vice president of GlobalFoundries’ silicon photonics product line. “We are excited to see Ayar Labs demonstrating the UCIe standard over an optical interface, a pivotal technology for scale-up networks. This accomplishment, uniquely enabled by our monolithic GF Fotonix™ platform, underscores the essential role of silicon photonics in driving highly energy efficient transmission of high-speed data over long distances while maintaining compatibility with chiplet-based standards.”
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TSMC: “Co-packaged optical (CPO) chiplets are set to transform the way we address data bottlenecks in large-scale AI computing. The availability of UCIe optical chiplets will foster a strong ecosystem, ultimately driving both broader adoption and continued innovation across the industry,” said Lucas Tsai, Vice President of Business Management at TSMC North America. “TSMC will continue our partnership with innovators like Ayar Labs to deliver CPO solutions with our silicon photonics technology, Compact Universal Photonic Engine (COUPE™), supporting the explosive growth in data transmission fueled by the AI boom.”
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UCIe Consortium: “The advancement of the UCIe standard marks significant progress toward creating more integrated and efficient AI infrastructure thanks to an ecosystem of interoperable chiplets,” said Dr. Debendra Das Sharma, Chair, UCIe Consortium. “By fostering interoperability and collaboration among vendors, UCIe provides the foundation to meet the growing demands for greater bandwidth and energy efficiency. It is incredibly encouraging to see Ayar Labs contribute to this momentum with this UCIe optical I/O chiplet.”
About Ayar Labs:
Ayar Labs provides optical interconnect solutions to accelerate data movement in large-scale AI infrastructure. Its standards-based optical technology combines the TeraPHY™ optical I/O chiplet and SuperNova™ multi-wavelength remote light source, optimizing compute efficiency while reducing latency, costs, and energy use. The technology supports composable architectures for AI training and inference applications.
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Source/Photo Credit: Ayar Labs
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